Title
Modelling And Simulation Of Off-Chip Communication Architectures For High-Speed Packet Processors
Keywords
Interconnect systems; k-Ary n-cube networks; Linecards; Memory management; Network processors; Shared-bus
Abstract
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications architectures for line cards. The simulator uses the state-of-the-art software design techniques to provide the user with a flexible, robust and comprehensive tool that can evaluate k-ary n-cube based network topologies under non-uniform traffic patterns. The simulator provides full control over essential network parameters and flow control mechanisms such as virtual channels and sub-channeling. We compare three low-dimensional k-ary n-cube based interconnects that can fit into the physical limitations on line cards, where each one of these interconnects has multiple processor-memory configurations. Performance results show that k-ary n-cube architectures perform better than existing interconnects, and they can sustain current line rates and higher. In addition, we provide performance tradeoffs between multiple flow control mechanisms and performance metrics such as throughput, routing accuracy, failure rate and interconnect utilization. © 2006 Elsevier Inc. All rights reserved.
Publication Date
12-1-2006
Publication Title
Journal of Systems and Software
Volume
79
Issue
12
Number of Pages
1701-1714
Document Type
Article
Personal Identifier
scopus
DOI Link
https://doi.org/10.1016/j.jss.2006.01.033
Copyright Status
Unknown
Socpus ID
33750931750 (Scopus)
Source API URL
https://api.elsevier.com/content/abstract/scopus_id/33750931750
STARS Citation
Engel, Jacob; Lacks, Daniel; and Kocak, Taskin, "Modelling And Simulation Of Off-Chip Communication Architectures For High-Speed Packet Processors" (2006). Scopus Export 2000s. 7828.
https://stars.library.ucf.edu/scopus2000/7828