Title

Clockless Pipelining For Coarse Grain Datapaths

Abstract

In this paper, we present two novel synchronization approaches to support data flow in clockless designs using single-rail encoding. Both approaches are based on self-resetting stage logic in which a pipeline stage resets itself before starting the next execution cycle. As such, a stage goes through a reset and an evaluate phase to complete a single period. While in the first approach synchronization is controlled between neighboring stages, the last stage of the pipeline in the second approach controls the synchronization of all the stages in the pipeline. Concept designs of both pipelines are presented to illustrate the inner workings of self-resetting stage logic and its data-flow synchronization mechanism. Implementation results show that both pipelines can reach throughputs up to 1.4 Giga outputs per second. © 2006 IEEE.

Publication Date

9-18-2006

Publication Title

Proceedings of the IEEE International Conference on VLSI Design

Volume

2006

Number of Pages

749-753

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/VLSID.2006.60

Socpus ID

33748542347 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/33748542347

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