Title

Parallel Hardware-Software Architecture For Computation Of Discrete Wavelet Transform Using The Recursive Merge Filtering Algorithm

Abstract

We present an FPGA -based parallel hardware-software architecture for the computation of the Discrete Wavelet Transform (DWT), using the Recursive Merge Filtering (RMF) algorithm. The DWT is built in a bottom-up fashion in logN steps, successively building complete DWTs by "merging" two smaller DWTs and applying the wavelet filter to only the "smooth" or DC coefficient from the smaller DWTs. The main bottleneck of this algorithm is the data routing process, which can be reduced by separating the computations into two types to introduce parallelism. This is achieved by using a virtual mapping structure to map the input. The data routing bottleneck has been transformed into simple arithmetic computations on the mapping structure. Due to the use of the FPGA -RAM for the mapping structure, the total number of data accesses to the main memory are reduced. This architecture shows how data routing in this problem can be transformed into a series of index computations. © 2000 Springer-Verlag Berlin Heidelberg.

Publication Date

1-1-2000

Publication Title

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volume

1800 LNCS

Number of Pages

250-256

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1007/3-540-45591-4_33

Socpus ID

84876398735 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84876398735

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