Title

Scalable Fpga Architecture For Dct Computation Using Dynamic Partial Reconfiguration

Keywords

DCT; Dynamic partial reconfiguration; FPGA

Abstract

In this paper, we propose FPGA-based scalable architecture for DCT computation using dynamic partial reconfiguration. Our architecture can achieve quality scalability using dynamic partial reconfiguration. This is important for some critical applications that need continuous hardware servicing. Our scalable architecture has two features. First, the architecture can perform DCT computations for eight different zones, i.e., from 1×1 DCT to 8×8 DCT. Second, the architecture can change the configuration of processing elements to trade off the precisions of DCT coefficients with computational complexity. Using dynamic partial reconfiguration with 2.1 MB bitstreams, 16 distinct hardware architectures can be implemented. We show the experimental results and comparisons between different configurations using both partial reconfiguration and non-partial reconfiguration process.

Publication Date

12-1-2008

Publication Title

Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008

Number of Pages

269-272

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

Socpus ID

62649168345 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/62649168345

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