Title

Bist-Based Group Testing For Diagnosis Of Embedded Fpga Cores

Keywords

DSP hard cores; Embedded cores; FPGA testing; Group testing; SOPC

Abstract

A group testing-based BIST technique to identify faulty hard cores in FPGA devices is presented. The method provides for isolation of faults in embedded cores as demonstrated by experiments on the Virtex-5 family of Xilinx FPGAs. High-level HDL code is developed to instantiate a Finite State Machine (FSM) which generates the test inputs for the Blocks Under Test (BUTs). The BUTs are divided into groups of four and at the end of a single stage of testing, up to 2 faulty BUTs are isolated successfully in each group of four. Experiments conducted show efficient fault isolation with a maximum of 30% area overhead under testing conditions. Isolation of faulty DSP cores is rapidly achieved without any permanent area cost. The approach can be readily extended to other embedded cores such as Block RAMs and Multipliers, thus providing a fast, efficient technique for testing prior to System On a Programmable Chip (SoPC) implementation on state of the art SRAM FPGAs.

Publication Date

12-1-2008

Publication Title

Proceedings of the 2008 International Conference on Embedded Systems and Applications, ESA 2008

Number of Pages

279-283

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

Socpus ID

62649143240 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/62649143240

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