Title

Segmented Digital Clock Manager- Fpga Based Digital Pulse Width Modulator Technique

Abstract

A new Digital Pulse Width Modulator (DPWM) design for a Field Programmable Gate Array (FPGA) based systems is presented in this paper. The proposed architecture fully utilizes the Digital Clock Manager (DCM) resources available on new FPGA boards. The proposed Segmented DCM DPWM is a digital modulator architecture with low power that allows for high switching frequency operation. It relies on the power-optimized resources already existing on new FPGAs. The inherit phase shifting properties of the DCM blocks simplify the duty cycle generation. The architecture can be applied to achieve various number of bits for the DPWM resolution, and is implemented and verified experimentally on a Virtex4 FPGA board. ©2008 IEEE.

Publication Date

9-29-2008

Publication Title

PESC Record - IEEE Annual Power Electronics Specialists Conference

Number of Pages

3036-3042

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/PESC.2008.4592415

Socpus ID

52349099555 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/52349099555

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