Title

Design Analysis Of Novel Substrate-Triggered Ggnmos In 65Nm Cmos Process

Abstract

A novel substrate-trigger GGNMOS structure with increasing the substrate resistance and pumping substrate trigger current using the VDD bus line controlled PMOS is proposed and verified in 65nm CMOS process. The trigger voltage can be significantly reduced to ∼3V to safely protect the ultrathin gate oxide. The proposed structure has lower overshoot voltage which is helpful to protect the ultrathin gate. The uniform conducting between multi-fingers has greatly enhanced and the failure current can effectively improved by 23.5% © 2010 IEEE.

Publication Date

9-15-2010

Publication Title

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Number of Pages

-

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/IPFA.2010.5532074

Socpus ID

77956426290 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/77956426290

This document is currently not available here.

Share

COinS