Title

Discriminatively Fortified Computing With Reconfigurable Digital Fabric

Keywords

Fault-tolerance; Fortified Computing; Redundancy allocation; Robustness

Abstract

This work proposes a novel approach- Discriminatively Fortified Computing (DFC)-to achieve hardware-efficient reliable computing without deterministically knowing the location and occurrence time of hardware defects and design faults. The key insights behind DFC comprise: 1) different system components contribute differently to the overall correctness of a target application, therefore should be treated distinctively, and 2) abundant error resilience exists inherently in many practical algorithms, such as signal processing, visual perception, and artificial learning. Such error resilience can be significantly improved with effective hardware support. The major contributions of this work include 1) the development of a complete methodology to perform sensitivity and criticality analysis of hardware redundancy, 2) a novel problem formulation and an efficient heuristic methodology to discriminatively allocate hardware redundancy among a target design's key components in order to maximize its overall error resilience, 3) an academic prototype of DFC computing device that illustrates a 4 times improvement of error resilience for a H.264 encoder implemented with an FPGA device. © 2011 IEEE.

Publication Date

12-1-2011

Publication Title

Proceedings of IEEE International Symposium on High Assurance Systems Engineering

Number of Pages

112-119

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/HASE.2011.49

Socpus ID

84856554635 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84856554635

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