Title

Self-Protection Capability Of Integrated Nldmos Power Arrays In Esd Pulse Regimes

Abstract

This paper provides a review of most recent cycle of studies of NLDMOS-based power arrays, their operation in ESD regimes, self-protection capability as well as the methods and measures to improve the array robustness on the device structure, layout architecture and array composition levels. Effective practices of improving ESD robustness at the cell level and backend level are presented followed by topology optimization. Discussion is based upon ESD characterization supported both by device-circuit mixed-mode and 2.5D array level simulations data. © 2011 Elsevier Ltd. All rights reserved.

Publication Date

1-1-2011

Publication Title

Microelectronics Reliability

Volume

51

Issue

12

Number of Pages

2015-2030

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1016/j.microrel.2011.05.017

Socpus ID

81855222059 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/81855222059

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