Title

Impact Of Soi Thickness On Fusi-Gate Cesl Cmos Performance And Reliability

Keywords

Compressive strain; contact etch stop layer (CESL); fully silicided (FUSI); gate oxide breakdown; hot electron; low-noise amplifier (LNA); negative bias temperature instability (NBTI); oxide trap charge; power amplifier; reliability; silicon on insulator (SOI); tensile strain

Abstract

The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided (FUSI)-metal-gate silicon-on-insulator (SOI) MOSFETs is investigated. High strain from a contact etch stop layer (CESL) in FUSI-gate transistors increases channel mobility and drain current driving. A CESL nMOSFET with a thick SOI demonstrates increased hot-electron degradation than its thin SOI counterpart. However, a ring oscillator using thick SOI transistors shows less gate delay due to enhanced drain current. Strained p-channel transistors with a large SOI thickness are more vulnerable to negative bias temperature instability. The oxide trap charge also plays an important role in the circuit performance degradation of RF low-noise and power amplifiers. © 2006 IEEE.

Publication Date

3-1-2011

Publication Title

IEEE Transactions on Device and Materials Reliability

Volume

11

Issue

1

Number of Pages

44-49

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/TDMR.2010.2072508

Socpus ID

79952830174 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/79952830174

This document is currently not available here.

Share

COinS