Title

Vftlp-VTh: A New Method For Quantifying The Effectiveness Of Esd Protection For The Cdm Classification Test

Abstract

A new methodology for quantifying the effectiveness of CDM protection circuits and CDM robustness of I/O circuits is presented in this paper. This method, referred to as the vfTLP-VTH, consists of applying vfTLP stresses to test structures composed of the ESD protection and the device or circuit to be protected: a MOS device or a MOS inverter. The protected structures are used as monitors and shifts in their characteristics, such as MOS threshold voltage VTH and saturation current IDD, are used to probe device failure criteria. © 2012 Elsevier Ltd. All rights reserved.

Publication Date

2-1-2013

Publication Title

Microelectronics Reliability

Volume

53

Issue

2

Number of Pages

196-204

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1016/j.microrel.2012.04.011

Socpus ID

84873744627 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84873744627

This document is currently not available here.

Share

COinS