Title
Challenges Of Designing Electrostatic Discharge (Esd) Protection In Modern And Emerging Cmos Technologies
Abstract
Electrostatic discharge (ESD) induced failures continue to be a major reliability concern in the semiconductor industry. Such a concern will in fact be intensified as the CMOS technology is scaling toward the 22-nm and beyond. This paper covers the issues and challenges pertinent to the design of electrostatic discharge (ESD) protection solutions of modern and future CMOS integrated circuits, including the highvoltage, low-voltage, and emerging nanowire technologies. © 2013 IEEE.
Publication Date
5-27-2013
Publication Title
ISNE 2013 - IEEE International Symposium on Next-Generation Electronics 2013
Number of Pages
1-3
Document Type
Article; Proceedings Paper
Personal Identifier
scopus
DOI Link
https://doi.org/10.1109/ISNE.2013.6512271
Copyright Status
Unknown
Socpus ID
84877999278 (Scopus)
Source API URL
https://api.elsevier.com/content/abstract/scopus_id/84877999278
STARS Citation
Liou, Juin J., "Challenges Of Designing Electrostatic Discharge (Esd) Protection In Modern And Emerging Cmos Technologies" (2013). Scopus Export 2010-2014. 6987.
https://stars.library.ucf.edu/scopus2010/6987