Title

Improving Memory Performance In Reconfigurable Computing Architecture Through Hardware-Assisted Dynamic Graph

Abstract

Being 'memory-centric', the single-chip distributed logic-memory (DLM) architecture can significantly improve the overall performance and energy efficiency of many memory-intensive embedded applications, especially those that exhibit irregular array data access patterns at algorithmic level. However, implementing DLM architecture poses unique challenges to an FPGA designer in terms of 1) organizing and partitioning diverse on-chip memory resources, and 2) orchestrating effective data transmission between on-chip and off-chip memory. In this paper, we offer our solutions to both of these challenges. Specifically, 1) we propose a stochastic memory partitioning scheme based on the well-known simulated annealing algorithm. It obtains memory partitioning solutions that promote parallelized memory accesses by exploring large solution space; 2) we augment the proposed DLM architecture with a reconfigure hardware graph that can dynamically compute precedence relationship between memory partitions, thus effectively exploiting algorithmic level memory parallelism on a per-application basis. © 2013 IEEE.

Publication Date

1-1-2013

Publication Title

2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013

Number of Pages

-

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ReConFig.2013.6732300

Socpus ID

84894487128 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84894487128

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