Title

Design-For-Security Vs. Design-For-Testability: A Case Study On Dft Chain In Cryptographic Circuits

Keywords

Design-for-Security; Hardware Trust

Abstract

Relying on a recently developed gate-level information assurance scheme, we formally analyze the security of design-for-test (DFT) scan chains, the industrial standard testing methods for fabricated chips and, for the first time, formally prove that a circuit with scan chain inserted can violate security properties. The same security assessment method is then applied to a built-in-self-test (BIST) structure where it is shown that even BIST structures can cause security vulnerabilities. To balance trustworthiness and testability, a new design-for-security (DFS) methodology is proposed which, through the modification of scan chain structure, can achieve high security without compromising the testability of the inserted scan structure. To support the task of secure scan chain insertion, a method of scan chain reshuffling is introduced. Using an AES encryption core as the testing platform, we elaborated the security assessment procedure as well as the DFS technique in balancing security and testability of cryptographic circuits.

Publication Date

9-18-2014

Publication Title

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Number of Pages

19-24

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ISVLSI.2014.54

Socpus ID

84908168038 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84908168038

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