Title

Applicability Of Power-Gating Strategies For Aging Mitigation Of Cmos Logic Paths

Keywords

aging; Bias Temperature Instability (BTI); low power design; MOSFET threshold-voltage shift; NBTI; PBTI; power-gating; sleep trasnsistor; voltage islands

Abstract

Aggressive CMOS technology scaling trends exacerbate the aging-related degradation of propagation delay and energy efficiency in nanoscale designs. Recently, Power-gating has been utilized as an effective low-power design technique which has also been shown to alleviate some aging impacts. However, the use of MOSFETs to realize power-gated designs will also encounter aging-induced degradations in the sleep transistors themselves which necessitates the exploration of design strategies to utilize power-gating effectively to mitigate aging. In particular, Bias Temperature Instability (BTI) which occurs during activation of power-gated voltage islands is investigated with respect to the placement of the sleep transistor in the header or footer as well as the impact of ungated input transitions on interfacial trapping. Results indicate the effectiveness of power-gating on NBTI/PBTI phenomena and propose a preferred sleep transistor configuration for maximizing higher recovery.

Publication Date

9-23-2014

Publication Title

Midwest Symposium on Circuits and Systems

Number of Pages

929-932

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/MWSCAS.2014.6908568

Socpus ID

84908483229 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84908483229

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