Title

High-Speed And Low-Power Fram With A Bitline-Segmental Array

Keywords

array; bitline-segmental; FRAM; power consumption; speed

Abstract

A bitline-segmental array architecture for ferroelectric random access memory (FRAM) is proposed to achieve lower power consumption and higher operation speed, in which the cell array is divided into four local blocks. Compared to the conventional array, the bitline-segmental arrays can decrease the power consumption by about 53 percent and 55 percent for read and write operation respectively. An experimental prototype utilizing the proposed architecture is implemented in 0.35 μ m 3-metal process and functionally verified.

Publication Date

3-13-2014

Publication Title

2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014

Number of Pages

-

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/EDSSC.2014.7061266

Socpus ID

84949924902 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84949924902

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