Title

Energy-Efficient Multiplier-Less Discrete Convolver Through Probabilistic Domain Transformation

Keywords

Discrete Convolution; Stochastic Logic

Abstract

Energy efficiency and algorithmic robustness typically are conflicting circuit characteristics, yet with CMOS technol-ogy scaling towards 10-nm feature size, both become criti-cal design metrics simultaneously for modern logic circuits. This paper propose a novel computing scheme hinged on probabilistic domain transformation aiming for both low power operation and fault resilience. In such a computing paradigm, algorithm inputs are first encoded through probabilistic means, which translates the input values into a number of random samples. Subsequently, light-weight operations, such as sim-ple additions will be performed onto these random samples in order to generate new random variables. Finally, the re-sulting random samples will be decoded probabilistically to give the final results. To validate the effectiveness of this proposed computing scheme, we presents a high-performance reconfigurable dis-crete convolver specifically designed for FPGA-based image and video processors. While the conventional multiplier-based architecture can only achieve O(N2), the proposed ar-chitecture, through the proposed probabilistic domain trans-formation, can achieve approximately O(N) in algorithmic complexity, therefore highly scalable and energy efficient. In addition, the PDT methodology makes the proposed archi-tecture highly fault-tolerant because information to be pro-cessed is encoded with probability density function instead of its binary forms. As such, the local perturbations of its computing accuracy or signal values are inconsequential to its overall results. The convolver prototype implemented with Virtex 6 FPGA devices (XC6VLX550t) requires just 4.09 s to perform a 128 128 convolution and dissipates only 166.63 nJ in dynamic energy consumption at 250 MHz. This new architecture can be exploited in all the real-time applications in which energy-efficient convolutions are re-quired and it can be realized with many other FPGA device families.

Publication Date

1-1-2014

Publication Title

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Number of Pages

185-188

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1145/2554688.2554769

Socpus ID

84898964309 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84898964309

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