Architecture And Circuit Design Of An All-Spintronic Fpga

Keywords

FPGA; MCell; Spintronic

Abstract

Reconfigurable logic device, such as FPGA, has been well-known to be the driver of cutting-edge device technology. In the last five years, there have been extensive studies on constructing novel FPGA devices using CMOS technology combined with emerging spintronic devices. Unfortunately, although spintronic device technology promises desirable features such as non-volatility and high area density, its relatively slow switching speed makes it quite challenging to use them as drop-in replacements for CMOS transistors. As such, to fully unlock the performance benefits of spintronic devices, it is imperative to develop innovative design techniques of circuit and architecture that are custom-made for building high-performance FPGA devices. In this paper, we aim at fully extracting the benefits of new spin-based device technology through innovative circuit and architecture design techniques for FPGAs. Specifically, we exploit the unique characteristics of a domain-wall logic device called the mCell to achieve a direct mapping to NAND-NOR logic and in doing so create a high-throughput non-volatile alternative to LUT-based CMOS reconfigurable logic. To empirically validate our approach, we have performed extensive HSpice circuit simulations. Our simulation results have shown that, for a similar logic capacity, the NAND-NOR FPGA design with mCell devices excels across all metrics when compared to the CMOS NAND-NOR FPGA design. Not only do we reduce average delay by about 17%, but we also improve path delay variance between different logic block configurations by about 59%, which can ease the burden on the FPGA timing analysis CAD tools by having more consistent delay between configurations. To judge the performance of our mCell FPGA in practical applications, we measured it against the Stratix IV LUT-based FPGA for the MCNC and VTR benchmark suites. Our mCell-based FPGA devices prove to be quite competitive against the CMOS LUT-based FPGA design, on average reducing delay and area by approximately 26% and 64% for the MCNC benchmark, and 13% and 55% for the VTR benchmark respectively.

Publication Date

2-15-2018

Publication Title

FPGA 2018 - Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Volume

2018-February

Number of Pages

41-50

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1145/3174243.3174256

Socpus ID

85052761909 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85052761909

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