Very Large-Scale And Node-Heavy Graph Analytics With Heterogeneous Fpga+Cpu Computing Platform

Keywords

FPGA; Graph analytics; Heterogeneous computing

Abstract

We present a highly scalable approach to constructing a reconfigurable computing engine specifically optimized to perform sophisticated kernel computing on graph-structured data. We choose newly emerged graph convolutional networks (GCNs) as our key benchmark and develop a novel node-heavy edge-centric computing framework for very large-scale graph analytics. Unlike most existing studies, our design and implementation can handle extremely large graph size that well exceeds the on-chip memory capacity of any FPGA+CPU heterogeneous platform, thus can only be stored in hard drive. The most novel aspect of our approach is to enable a completely streaming mode of large vertex and edge data and perform a write-back message updating policy, therefore completely removing any redundant data accesses to IO-expensive hard drive. Additionally, our subgraph sorting scheme can effectively eliminate the performance bottleneck caused by preprocessing in the state-of-Art computing framework X-Stream. To validate our approach, we have implemented our proposed method with a KC705 Xilinx FPGA board and tested it with multiple real-world large-scale data sets. For the largest data set with 210,010 vertices and 1,349,400 edges, our platform achieves 1.87s in total latency, which is approximately 400 times faster than the baseline platform with the state-of-The-Art approach.

Publication Date

8-7-2018

Publication Title

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volume

2018-July

Number of Pages

638-643

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ISVLSI.2018.00121

Socpus ID

85052085037 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85052085037

This document is currently not available here.

Share

COinS