Fabless Design Approach For Lateral Optimization Of Low Voltage Gan Power Hemts

Keywords

Double heterostructure field effect transistor (DHFET); Fabless design; Figure of merit optimization; GaN HEMT; Power devices

Abstract

This paper demonstrates a fabless design approach for the lateral optimization of a low voltage GaN power HEMT. Optimization of lateral scaling terms such as gate-to-drain, gate, and gate-to-source lengths allows for minimization of the figure-of-merit (RDS(on) × QG) for a targeted breakdown voltage. Results show a FOM of 11 mΩ-nC for a device with a breakdown voltage >50 V. These results are for a given heterostructure design and estimated trap densities, and the effects of changing these estimated trap densities have been demonstrated to heavily influence breakdown behavior. As such, the focus of this study is on the relative difference between results rather than the absolute numbers. For this given design, results suggest that by shrinking LGD further the FOM can be reduced to 6.68 mΩ-nC with a breakdown of 71 V: representing a 74% decrease in FOM compared to the EPC 2023 device (30 V device) [1].

Publication Date

9-1-2018

Publication Title

Superlattices and Microstructures

Volume

121

Number of Pages

92-106

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1016/j.spmi.2018.07.026

Socpus ID

85053141542 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85053141542

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