Design And Analysis Of An Area-Efficient High Holding Voltage Esd Protection Device

Keywords

Area efficiency; Double snapback phenomenon; Floating p+; Gate-grounded nMOS (GGnMOS) incorporated silicon-controlled rectifier (GGISCR); High holding voltage

Abstract

A novel electrostatic discharge protection device gate-grounded nMOS (GGnMOS) incorporated silicon-controlled rectifier (GGISCR) is proposed in this paper. With a distinguished feature of an imbedded floating P+ region, the GGISCR is demonstrated to be superior to the conventional low voltage triggered SCR and GGnMOS in terms of high area efficiency and high holding voltage. The operational mechanism of GGISCR device is discussed in detail, and the effect of floating P+ region on the GGISCR's I-V characteristics is analyzed via TCAD simulation results as well.

Publication Date

2-1-2015

Publication Title

IEEE Transactions on Electron Devices

Volume

62

Issue

2

Number of Pages

606-614

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/TED.2014.2381511

Socpus ID

84921744170 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84921744170

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