A Dynamic, Linearly-Shifted, Fixed-Slope Digital-Ramp Control Technique For Improved Transient Response In Dc - Dc Converters

Keywords

Counter - Comparator; DC - DC converter; Digital Control; FPGA; PWM; transient response

Abstract

A conventional Counter-Comparator Digital Pulse Width Modulator (DPWM) with a fixed slope is dynamically and linearly shifted upwards or downwards by a value proportional to the error signal. The shift is done through applying a positive or negative offset (shift) value depending on the direction of the transient. This control approach aims to improve the transient response and efficiency of an FPGA-based digitally controlled DC-DC converters in terms of shorter settling time with optimal over-and undershoots. The dynamic Ramp Shift design method presented in this work is a linear DC shift control achieving a better dynamics response through reducing the time required by the compensator to reach back to the steady state during a transient condition. Moreover, it utilizes existing system digital controller, and does not require any additional circuitry. This shifting will only occur during transients for the reason that the error (which basically formulates the shift value) is almost zero during steady state, while during transients; the positive or negative value of the error will shift the ramp downwards or upwards. The proposed digital technique is validated by computer simulation. Experimental result of a prototype on a Xilinix FPGA platform verifies the concept.

Publication Date

12-29-2015

Publication Title

2015 4th International Conference on Electric Power and Energy Conversion Systems, EPECS 2015

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/EPECS.2015.7368498

Socpus ID

84964702223 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84964702223

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