Self-Scaling Evolution Of Analog Computation Circuits With Digital Accuracy Refinement

Keywords

Accuracy; Analog circuits; Fabrics; Genetic algorithms; Genomics; Sociology; Statistics

Abstract

We introduce SCALER, a two-pronged strategy utilizing digital resources for refining intrinsic evolution of analog computational circuits. A Self-Scaling Genetic Algorithm is proposed to adapt solutions to computationally-tractable ranges in hardware-constrained analog reconfigurable fabrics. Differential Digital Correction is developed utilizing an error metric computed from the evolved analog circuit to reconfigure the digital fabric intrinsically thereby enhancing precision. We demonstrate our methods by evolving square, square-root, cube, and cube-root analog computational circuits on the Cypress PSoC-5LP System-on-Chip. Results indicate that the Self-Scaling Genetic Algorithm improves an error metric on average 7.18-fold, up to 12.92-fold for computational circuits that produce outputs beyond device range. Overall, Differential Digital Correction can reduce computational error by 23.1% compared to the performance of the evolved analog circuit.

Publication Date

8-31-2015

Publication Title

2015 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2015

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/AHS.2015.7231174

Socpus ID

84962497956 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84962497956

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