Designing Energy-Efficient Approximate Adders Using Parallel Genetic Algorithms

Keywords

adder; adders; approximate computing; delay; error distance; genetic algorithms; inexact arithmetic units; low power; parallel genetic algorithm; parallelism; power consumption; power reduction; process variation; variable accuracy

Abstract

Approximate computing involves selectively reducing the number of transistors in a circuit to improve energy savings. Energy savings may be achieved at the cost of reduced accuracy for signal processing applications whereby constituent adder and multiplier circuits need not generate a precise output. Since the performance versus energy savings landscape is complex, we investigate the acceleration of the design of approximate adders using parallelized Genetic Algorithms (GAs). The fitness evaluation of each approximate adder is explored by the GA in a non-sequential fashion to automatically generate novel approximate designs within specified performance thresholds. This paper advances methods of parallelizing GAs and implements a new parallel GA approach for approximate multi-bit adder design. A speedup of approximately 16-fold is achieved using a quad-core Intel processor and results indicate that the proposed GA is able to find adders which consume 63:8% less energy than accurate adders.

Publication Date

6-24-2015

Publication Title

Conference Proceedings - IEEE SOUTHEASTCON

Volume

2015-June

Issue

June

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/SECON.2015.7132970

Socpus ID

84938099710 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84938099710

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