Parallel Computing Using Memristive Crossbar Networks: Nullifying The Processor-Memory Bottleneck

Abstract

We are quickly reaching an impasse to the number of transistors that can be squeezed onto a single chip. This has led to a scramble for new nanotechnologies and the subsequent emergence of new computing architectures capable of exploiting these nano-devices. The memristor is a promising More-than-Moore device because of its unique ability to store and manipulate data on the same device. In this paper, we propose a flexible architecture of memristive crossbar networks for computing Boolean formulas. Our design nullifies the gap between processor and memory in von Neumann architectures by using the crossbar both for the storage of data and for performing Boolean computations. We demonstrate the effectiveness of our approach on practically important computations, including parallel Boolean matrix multiplication.

Publication Date

2-10-2015

Publication Title

Proceedings of 2014 9th International Design and Test Symposium, IDT 2014

Number of Pages

147-152

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/IDT.2014.7038603

Socpus ID

84924301845 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84924301845

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