Reactive Rejuvenation Of Cmos Logic Paths Using Self-Activating Voltage Domains

Keywords

aging-critical domain; BTI-inducing aging; CMOS reliability; critical logic paths; Dynamic Voltage Scaling (DVS); reactive aging mitigation

Abstract

Although the trend of technology scaling is sought to realize higher performance computer systems, it also results in Integrated Circuits (ICs) suffering from increasing Process, Voltage, and Temperature (PVT) variations and adverse aging effects. In most cases, these reliability threats manifest themselves as timing errors on critical speed-paths of the circuit, if a large design guardband is not reserved. In this work, we propose the Reactive Rejuvenation (RR) architectural approach consisting of detection and recovery phases to mitigate circuit from BTI-induced aging. The BTI impact on the critical and near critical paths performance is continuously examined through a lightweight logic circuit which asserts an error signal in the case of any timing violation in those paths. By utilizing timing violation occurrence in the system, the timing-sensitive portion of the circuit is recovered from BTI through switching computations to redundant aging-critical voltage domain. The proposed technique achieves aging mitigation and reduced energy consumption as compared to a baseline circuit. Thus, significant voltage guardbands to meet the desired timing specification are avoided.

Publication Date

7-27-2015

Publication Title

Proceedings - IEEE International Symposium on Circuits and Systems

Volume

2015-July

Number of Pages

2944-2947

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ISCAS.2015.7169304

Socpus ID

84946202539 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84946202539

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