Fir Filter Based On Stochastic Computing With Reconfigurable Digital Fabric

Keywords

FIR filter; FPGA; Stochastic computing

Abstract

FIR filtering is widely used in many important DSP applications in order to achieve filtering stability and linear-phase property. This paper presents a hardware-and energy-efficient approach to implement FIR filtering through reconfigurable stochastic computing. Specifically, we exploit a basic probabilistic principle of summing independent random variables to achieve approximate FIR filtering without costly multiplications. This allows our proposed FIR architecture to achieve about 9 times and 4 times less power consumption than the conventional multiplier-based and DA-based design, respectively. Additionally, when compared with the state-of-the art systolic DA-based design, our design can achieve about 3times reduction in hardware usage.

Publication Date

7-15-2015

Publication Title

Proceedings - 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015

Number of Pages

92-95

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/FCCM.2015.32

Socpus ID

84943411143 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84943411143

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