A Tunable Majority Gate-Based Full Adder Using Current-Induced Domain Wall Nanomagnets

Keywords

Domain wall (DW) motion; domain wall nanomagnet (DWNM); high density logic; magnetic full adder (FA); Magnetic majority gate (MG)

Abstract

Domain wall nanomagnet (DWNM)-based devices have been extensively studied as a promising alternative to the conventional CMOS technology in both the memory and logic implementations due to their non-volatility, near-zero standby power, and high integration density characteristics. In this paper, we leverage a physics-based model of a DWNM device to design a highly scalable current-mode majority gate to achieve a novel one bit full-adder (FA) circuit. The modeled DWNM specifications are calibrated with the experimentally measured data. The functionality of the proposed DWNM-based FA (DWNM-FA) is verified using a SPICE circuit simulator. The detailed analysis and the calculations have been performed to realize the proposed DWNM-FA delay and power consumption corresponding to the various induced input currents at different operating temperatures. The power-delay product of DWNM-FA is examined to tune the operation within the optimum induced input current region to obtain desired power-delay requirements over a range of 200 μA to 1 mA at temperatures from 298 to 378 K. Finally, the comparison results exhibit 52% and 49% area improvement as well as 41% and 31% improvement in device count complexity over CMOS-based and magnetic tunnel junction-based FA designs, respectively.

Publication Date

8-1-2016

Publication Title

IEEE Transactions on Magnetics

Volume

52

Issue

8

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/TMAG.2016.2540600

Socpus ID

84979640086 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84979640086

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