Loss-Aware Switch Design And Non-Blocking Detection Algorithm For Intra-Chip Scale Photonic Interconnection Networks

Keywords

Chip multiprocessors; Integrated optoelectronics; Interconnection networks; Network performance; Non-blocking photonic switch; Optical losses

Abstract

As the number of on-chip processor cores increases, power-efficient solutions are sought for data communication between cores. The Helix-h non-blocking photonic switch is developed to improve physical-layer and network performance parameters for a wide range of silicon nano-photonic multicore interconnection topologies. Traffic benchmarks and practical case studies using a cycle-accurate simulation environment indicate significantly reduced insertion loss providing improved bandwidth density and scalability to manycore plurality. Improvements in system performance parameters are quantified for network bandwidth, transmission efficiency, and latency in popular photonic internconnection topologies, in comparison to previous switch designs. For instance, utilizing the Helix-h switch in a mesh topology, the bandwidth is increased by 112 percent compared to the previously highest performing switch design. Execution time and energy efficiency are improved by up to 92 and 99 percent, respectively, for representative multicore applications. Finally, the technique is generalized to a novel graph-theoretic method for articulating blocking conditions in photonic switches.

Publication Date

6-1-2016

Publication Title

IEEE Transactions on Computers

Volume

65

Issue

6

Number of Pages

1789-1801

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/TC.2015.2458866

Socpus ID

84969766625 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84969766625

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