Processing Effect On Via Extrusion For Tsvs In Three-Dimensional Interconnects: A Comparative Study
Keywords
Electroplating; Thermal stress; Through-silicon via (TSV); Via extrusion
Abstract
A comparative study has been performed to investigate the processing effects on via extrusion for through-silicon vias (TSVs) in 3-D integration. This paper is focused on three TSV structures with identical geometry but different processing conditions. The thermomechanical behavior, microstructure, via extrusion, and additives incorporated during electroplating are examined by various techniques, including the electron backscatter diffraction and the time-of-flight secondary ionmass spectroscopy. By comparing the stress, material, and via extrusion behaviors of the TSV structures, the effect of processing conditions, particularly electroplating and postplating annealing, on via extrusion are discussed.
Publication Date
12-1-2016
Publication Title
IEEE Transactions on Device and Materials Reliability
Volume
16
Issue
4
Number of Pages
465-469
Document Type
Article
Personal Identifier
scopus
DOI Link
https://doi.org/10.1109/TDMR.2016.2591945
Copyright Status
Unknown
Socpus ID
85003952909 (Scopus)
Source API URL
https://api.elsevier.com/content/abstract/scopus_id/85003952909
STARS Citation
Jiang, Tengfei; Spinella, Laura; Im, Jang Hi; Huang, Rui; and Ho, Paul S., "Processing Effect On Via Extrusion For Tsvs In Three-Dimensional Interconnects: A Comparative Study" (2016). Scopus Export 2015-2019. 3278.
https://stars.library.ucf.edu/scopus2015/3278