Compact Failure Modeling For Devices Subject To Electrostatic Discharge Stresses - A Review Pertinent To Cmos Reliability Simulation

Keywords

Electrostatic discharge (ESD); Gate oxide breakdown; Junction thermal failure; Thermal network; Transient power law (TPL); Transmission line pulsing (TLP)

Abstract

This paper reviews the physical mechanisms and compact modeling approaches of two physical damages in MOS devices induced by electrostatic discharge (ESD) stresses; namely gate oxide breakdown and thermal failures. Theories underlying the failure mechanism are discussed and compact models that can be used to monitor ESD induced gate oxide breakdown and thermal failure are developed. Related work reported in the literature is discussed, and benchmarking of measurement data versus simulation results are included in support of the modeling work.

Publication Date

1-1-2015

Publication Title

Microelectronics Reliability

Volume

55

Issue

1

Number of Pages

15-23

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1016/j.microrel.2014.10.015

Socpus ID

84920510141 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84920510141

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