Hardware Design And Verification Techniques For Supply Chain Risk Mitigation

Creator

Bao Liu, The University of Texas at San Antonio
Yier Jin, University of Central Florida
Gang Qu, A. James Clark School of Engineering

Abstract

We present a brief survey on the state-of-the-art design and verification techniques: IC obfuscation, watermarking, fingerprinting, metering, concurrent checking and verification, for mitigating supply chain security risks such as IC misusing, counterfeiting and overbuilding.

Publication Date

4-8-2016

Publication Title

Proceedings - 2015 14th International Conference on Computer-Aided Design and Computer Graphics, CAD/Graphics 2015

Number of Pages

238-239

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/CADGRAPHICS.2015.53

Copyright Status

Unknown

Socpus ID

84971452278 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84971452278

STARS Citation

Liu, Bao; Jin, Yier; and Qu, Gang, "Hardware Design And Verification Techniques For Supply Chain Risk Mitigation" (2016). Scopus Export 2015-2019. 4336.
https://stars.library.ucf.edu/scopus2015/4336