Title

Enhancing Hardware Security With Emerging Transistor Technologies

Keywords

Emerging transistors; Hardware security; IC camouflaging; NCFET; Polymorphic logic; SymFET; TFET; Tunnel transistor

Abstract

We consider how the I-V characteristics of emerging transistors (particularly those sponsored by STARnet) might be employed to enhance hardware security. An emphasis of this work is to move beyond hardware implementations of physically unclonable functions (PUFs) and random number generators (RNGs). We highlight how new devices (i) may enable more sophisticated logic obfuscation for IP protection, (ii) could help to prevent fault injection attacks, (iii) prevent differential power analysis in lightweight cryptographic systems, etc.

Publication Date

5-18-2016

Publication Title

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volume

18-20-May-2016

Number of Pages

305-310

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1145/2902961.2903041

Socpus ID

84974733887 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84974733887

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