Ultra-Low Energy Reconfigurable Spintronic Threshold Logic Gate

Keywords

Magnetic domain wall strip; Magnetic tunnel junction; Reconfigurable logic; Spintronic; Threshold logic

Abstract

This paper introduces a novel design of reconfigurable Spintronic Threshold Logic Gate (STLG), which employs spintronic weight devices to perform current mode weighted summation of binary inputs, whereas, the low voltage spintronic threshold device carries out the thresholding operation in an energy efficient manner. The proposed STLG can operate at a small terminal voltage of ∼50mV, resulting in ultra-low energy consumption. The device-circuit simulation results for common benchmarks show that the proposed STLG circuit can achieve 87.5% and 11.1% energy reduction compared with state-of-the-art CMOS look-up-table (LUT) and Memristive Threshold Logic Gate (MTLG) respectively. The ultra-low programming energy of spintronic weight device also leads to three orders lower reconfiguration energy of STLG compared with MTLG design.

Publication Date

5-18-2016

Publication Title

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volume

18-20-May-2016

Number of Pages

385-388

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1145/2902961.2902994

Socpus ID

84974717552 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84974717552

This document is currently not available here.

Share

COinS