Scaling Effect Of Through-Silicon Via (Tsv) On Stress And Reliability For 3D Interconnects
Keywords
Extrusion; Microstructure; Reliability; Scaling; Stress; TSV
Abstract
Through-silicon vias (TSVs) enable full three-dimensional integration by providing high-density vertical interconnections for improved device bandwidth and power consumption. However, TSVs pose unique reliability risks due to via extrusion, which is caused by thermal stress induced by the mismatch in the coefficients of thermal expansion (CTE) for the silicon and the copper. These effects can degrade device performance and it has been proposed that optimal post-plating annealing and shrinking via dimensions can be effective in mitigating negative stress effects for TSVs. In this paper, the scaling effect on TSV stress and reliability is investigated by examining the evolution of the copper microstructure during annealing and its effect on the plasticity and extrusion statistics for 10, 5, and 2μm-diameter TSVs. TSV stress and plasticity are correlated to the cross-sectional microstructure using synchrotron x-ray microdiffraction and electron backscatter diffraction. Annealing was found to increase scatter in the grain size distribution and in the via extrusion statistics, as well as significantly increase the extrusion heights for each TSV set. These results can be traced to the elastic anisotropy of copper, as the abnormal grain growth, which increases the statistical spreads in the via extrusion distributions and is controlled by the strain energy originating from the CTE mismatch. Interestingly, the results from the 2μm-diameter TSVs offer no advantages over larger TSVs, as additional annealing to 400°C was found to increase the statistical variability in grain structure and via extrusion. Since such annealing processes are required for via-middle fabrication, it seems that via reliability will continue to be a challenge as TSV scaling continues.
Publication Date
3-1-2017
Publication Title
Advancing Microelectronics
Volume
44
Issue
2
Number of Pages
12-15
Document Type
Article
Personal Identifier
scopus
Copyright Status
Unknown
Socpus ID
85019888035 (Scopus)
Source API URL
https://api.elsevier.com/content/abstract/scopus_id/85019888035
STARS Citation
Spinella, Laura; Im, Jang Hi; Ho, Paul S.; and Jiang, Tengfei, "Scaling Effect Of Through-Silicon Via (Tsv) On Stress And Reliability For 3D Interconnects" (2017). Scopus Export 2015-2019. 4782.
https://stars.library.ucf.edu/scopus2015/4782