28 Nm Cmos Process Esd Protection Based On Diode-Triggered Silicon Controlled Rectifier

Keywords

DTSCR; Failure analysis; Robustness; TLP

Abstract

The downsizing of CMOS technology into the decananometer range has called for the redesign of the ESD protection devices because of the constraints of lower operation voltage and smaller breakdown voltage of the ultrathin gate oxide. In this work, we had developed a two-dimensional diode-triggered silicon-controlled rectifier (TD-DTSCR) structure to cope with the narrowed ESD design window in the 28 nm CMOS technology. A sufficient large SCR trigger voltage was obtained by directing the triggering current to both longitude and lateral directions, through two parasitic diodes and the P-Well, so as to save the chip area for realization. Optimization was done by varying several device parameters and the best ESD robustness obtained was 53.7 mA/μm which was about 65% larger than that of a simple SCR with the same width of 30 μm and realized using the same technology. Failure analysis was also conducted to identify the possible weak spots of the proposed structure.

Publication Date

11-1-2017

Publication Title

Solid-State Electronics

Volume

137

Number of Pages

128-133

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1016/j.sse.2017.07.012

Socpus ID

85029545733 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85029545733

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