Title

Ip Trust Validation Using Proof-Carrying Hardware

Keywords

Formal Verification; Hardware IP; IP Protection; Proof-Carrying Hardware; System-on-Chip

Abstract

The wide usage of hardware Intellectual Property (IP) cores from untrusted third-party vendors has raised security vulnerabilities at design stages of the IC design flow. Possibility of hardware Trojans and/or design backdoors in the IP cores has increased security concerns. As existing functional testing methods fall short in detecting these unspecified (often malicious) logic, formal methods provide powerful solutions in detecting malicious behaviors in hardware. Toward this direction, we will discuss theorem proving and model checking for hardware trust evaluation. Specifically, proof-carrying hardware (PCH) and its applications are introduced in detail. While PCH methods suffer from scalability issues and cannot be easily used for large-scale applications such as System-on-Chip (SoC) design, we will also discuss variants of PCH such as the Hierarchy Preserving Formal Verification framework, for alleviating the scalability challenge.

Publication Date

1-1-2017

Publication Title

Hardware IP Security and Trust

Number of Pages

207-225

Document Type

Article; Book Chapter

Personal Identifier

scopus

DOI Link

https://doi.org/10.1007/978-3-319-49025-0_10

Socpus ID

85042843772 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85042843772

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