Revisit Sequential Logic Obfuscation: Attacks And Defenses

Abstract

The urgent requests to protection integrated circuits (IC) and hardware intellectual properties (IP) have led to the development of various logic obfuscation methods. While most existing solutions focus on the combinational logic or sequential logic with full scan-chains, in this paper, we will revisit the security of sequential logic obfuscation within circuits where full scan-chains are not available or accessible. We will first introduce attack methods to compromise obfuscated sequential circuits leveraging newly developed netlist analysis tools. We will then propose systematic solutions and provide guidelines in developing resilient sequential logic obfuscation schemes.

Publication Date

9-25-2017

Publication Title

Proceedings - IEEE International Symposium on Circuits and Systems

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ISCAS.2017.8050606

Socpus ID

85032654635 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85032654635

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