Avoiding Tlb Shootdowns Through Self-Invalidating Tlb Entries

Keywords

Heterogeneous Memory; HW/SW Co-design; NonVolatile Memories; Self-Invalidation; TLB; TLB Shootdown; Virtual Memory

Abstract

Updates to a process's page table entry (PTE) renders any existing copies of that PTE in any of a system's TLBs stale. To prevent a process from making illegal memory accesses using stale TLB entries, the operating system (OS) performs a costly TLB shootdown operation. Rather than explicitly issuing shootdowns, we propose a coordinated TLB and page table management mechanism where an expirationtime is associated with each TLB entry. An expired TLB entry is treated as invalid. For each PTE, the OS then tracks the latest expiration time of any TLB entry potentially caching that PTE. No shootdown is issued if the OS modifies a PTE when its corresponding latest expiration time has already passed.In this paper, we explain the hardware and OS support required to support Self-invalidating TLB entries (SITE). As an emerging use case that needs fast TLB shootdowns, we consider memory systems consisting of different types of memory (e.g., faster DRAM and slower non-volatile memory) where aggressive migrations are desirable to keep frequently accessed pages in faster memory, but pages cannot migratetoo often because each migration requires a PTE update and corresponding TLB shootdown. We demonstrate that such heterogeneous memory systems augmented with SITE can allow an average performance improvement of 45.5% over a similar system with traditional TLB shootdowns by avoiding more than 65% of the shootdowns.

Publication Date

10-31-2017

Publication Title

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volume

2017-September

Number of Pages

273-287

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/PACT.2017.38

Socpus ID

85032288708 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85032288708

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