A Compact 8-Bit Adder Design Using In-Memory Memristive Computing: Towards Solving The Feynman Grand Prize Challenge

Abstract

We introduce a new compact in-memory computing design for implementing 8-bit addition using eight vertically-stacked nanoscale crossbars of one-diode one-memristor 1D1M switches. Each crossbar in our design only has 5 rows and 4 columns. Hence, the design may be used to fabricate a compact 8-bit adder that meets the size constraint of 50nm χ 50nm χ 50nm imposed by the electrical component of the Feynman Grand Prize. The potential availability of sub-5nm nanoscale memristors and single-molecule diode devices coupled with the ability to fabricate high-density nanoscale memristor crossbars suggests that our design may eventually be fabricated to meet the size constraints of the Feynman Grand Prize.

Publication Date

9-28-2017

Publication Title

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017

Number of Pages

67-72

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/NANOARCH.2017.8053712

Socpus ID

85034763040 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85034763040

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