A 300 Mv, 6-Bit Ultra-Low Power Sar Adc

Keywords

Analog-to-digital converter (ADC); Successive approximation register; Temperature-stabiliby; Ultra-low power; Ultra-low voltage

Abstract

This work uses the mutual temperature compensation of threshold voltage and carrier mobility to establish the optimum overdrive voltage for a MOS transistor. A fully differential SAR ADC is designed using 65 nm technology with improved temperature and process stability and can work under supply voltage of 300 mV. Simulation results show that under VDD of 300 mV the ADC is able to achieve a peak ENOB of 5.5 bits, with a variation of 0.7 bit over temperature range of-55 °C to 125 °C. Also the FOM of the ADC is 8.8 and 58 fJ/conversion-step at 27 °C and 125 °C, respectively.

Publication Date

7-31-2017

Publication Title

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings

Number of Pages

713-715

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ICSICT.2016.7999020

Socpus ID

85028669654 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85028669654

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