High Performance And Energy-Efficient In-Memory Computing Architecture Based On Sot-Mram

Keywords

AES; in-memory computing; SOT-MRAM

Abstract

In this paper, we propose a novel Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array design that could either work as non-volatile memory or implement a reconfigurable in-memory logic (AND/OR/XOR) without addon logic circuits to memory chip as in conventional logic-in-memory designs. The computed logic output could be simply read out like a typical MRAM bit-cell through the modified memory peripheral circuits. Such intrinsic in-memory logic could be used to process data locally to greatly reduce power-hungry and long distance data communication in conventional Von Neumann computing systems. In this work, we further employ in-memory data encryption using Advanced Encryption Standard (AES) algorithm as a case study to demonstrate the efficiency of the proposed design. The device to architecture co-simulation results show that the proposed in-memory data encryption design can achieve 71.2% and 17.3% lower energy consumption compared to CMOS-ASIC and recent Domain Wall (DW)-AES implementations, respectively. Furthermore, it shows ∼ 33% reduction in area compared to DW-AES.

Publication Date

9-28-2017

Publication Title

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017

Number of Pages

97-102

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/NANOARCH.2017.8053725

Socpus ID

85034760173 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85034760173

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