Title
Comprehensive Study Of Esd Design Window Scaling Down To 7Nm Technology Node
Abstract
ESD design window for mainstream bulk and SOI planar/FinFET technologies across 350nm- 7nm node are compared for the first time. 100ns TLP and 1ns vfTLP characteristics of Vgox, Vt1, and It2 of various logic and I/O FETs are presented and discussed. Expanding the design window by utilizing series resistance within I/O drivers is discussed.
Publication Date
10-25-2018
Publication Title
Electrical Overstress/Electrostatic Discharge Symposium Proceedings
Volume
2018-September
Document Type
Article; Proceedings Paper
Personal Identifier
scopus
Copyright Status
Unknown
Socpus ID
85056830289 (Scopus)
Source API URL
https://api.elsevier.com/content/abstract/scopus_id/85056830289
STARS Citation
Dong, Aihua; Xiong, Jie; Mitra, Souvick; Liang, Wei; and Gauthier, Robert, "Comprehensive Study Of Esd Design Window Scaling Down To 7Nm Technology Node" (2018). Scopus Export 2015-2019. 7637.
https://stars.library.ucf.edu/scopus2015/7637