High-Performance Double Node Upset-Tolerant Non-Volatile Flip-Flop Design

Keywords

Double node upset (DNU); emerging devices; magnetic tunnel junction (MTJ); non-volatile flip-flop (NVFF); reliability; single-event upset (SEU); soft-error

Abstract

Emerging spin-based devices are introduced as an intriguing candidate to alleviate leakage currents and continue the scalability of CMOS technology. However, their immunity to radiation-induced transient faults needs to be adequately addressed. In this work, a radiation-immune hybrid Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ)/CMOS flip-flop is designed and evaluated for nonvolatile applications. The proposed nonvolatile flip-flop circuit achieves attractive features, such as low standby power dissipation (21% less than CMOS-based design), high computing performance, and superior soft-error resilience (concurrently can tolerate DNU) to potentially become as a mainstream solution for the aerospace and avionic nanoelectronics.

Publication Date

10-1-2018

Publication Title

Conference Proceedings - IEEE SOUTHEASTCON

Volume

2018-April

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/SECON.2018.8478941

Socpus ID

85056129576 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85056129576

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