Imcs2: Novel Device-To-Architecture Co-Design For Low-Power In-Memory Computing Platform Using Coterminous Spin Switch

Keywords

Giant spin Hall effect (GSHE); in-memory computing; memory architecture; reconfigurable logic; spin switch (SS)

Abstract

Spin switch (SS) is a promising spintronic device which exhibits compactness, low power, non-volatility, input-output isolation leveraging giant spin Hall effect, spin transfer torque, and dipolar coupling. In this paper, we propose a novel device-to-architecture co-design for an in-memory computing platform using coterminous SS (IMCS2), which could simultaneously work as non-volatile memory and reconfigurable in-memory logic (AND/NAND, OR/NOR, and XOR/XNOR) without add-on logic circuits to memory chip. The computed logic output could be simply read out like a normal magnetic random access memory bit cell using the shared memory peripheral circuits. Such intrinsic in-memory logic could be used to process data within memory to greatly reduce power-hungry and long distance data communication in the conventional von Neumann computing system. The IMCS2-based in-memory bulk bitwise Boolean vector operation shows ∼9× energy saving and ∼3× speedup compared with that of DRAM-based in-memory computing platform. We further employ in-memory multiplication to evaluate the performance of the proposed in-memory computing platform for vector-vector multiplication with different vector sizes.

Publication Date

7-1-2018

Publication Title

IEEE Transactions on Magnetics

Volume

54

Issue

7

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/TMAG.2018.2819959

Socpus ID

85045753891 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85045753891

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