Slim-Adc: Spin-Based Logic-In-Memory Analog To Digital Converter Leveraging She-Enabled Domain Wall Motion Devices

Keywords

Beyond-CMOS devices; Boolean logic; In-memory computation; Signal conversion; Spin-Hall Effect Domain Wall Motion

Abstract

This paper devises a novel Analog to Digital Converter (ADC) framework for energy-aware acquisition of analog signals with Logic-in-Memory capabilities. The beyond-CMOS hardware architecture has been designed to minimize the overall cost of signal acquisition. Spin-Hall Effect driven Domain Wall Motion (SHE-DWM) devices are utilized to realize the proposed framework called Spin-based Logic-In-Memory ADC (SLIM-ADC). Our simulation results indicate that the proposed SLIM-ADC offers ∼200 fJ energy consumption on average for each analog conversion or logic operation with up to 1 GHz speed. Furthermore, our results indicate that the proposed SLIM-ADC outperforms other state of the art spin-based ADC designs by offering ∼5.45 mW improved power dissipation on average. Additionally, a Majority Gate (MG)-based Full-Adder (MG-FA) is implemented using the proposed SLIM-ADC. Our results show that the proposed MG-FA offers ∼2.9-fold reduced power dissipation on average and ∼1.7-fold reduced delay on average compared to the state of the art Full-Adder designs reported herein.

Publication Date

11-1-2018

Publication Title

Microelectronics Journal

Volume

81

Number of Pages

137-143

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1016/j.mejo.2018.09.012

Socpus ID

85054573704 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85054573704

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