Promoting Mlc Stt-Ram For The Future Persistent Memory System

Abstract

As the memory wall issue continues in the era of big data, researchers have been exploring emerging technologies to replace or complement the current DRAM based main memory system. Among them, Multi-Level Cell (MLC) configurations of Spin-Transfer Torque Random Access Memory (STT-RAM) attracts tremendous interests and has been deployed as the onchip cache successfully. In this paper, we discuss the possibilities and challenges of employing MLC STT-RAM in the future persistent memory system. We also propose a hybrid data block to bit mapping strategy called Double-S to promote the use of soft bit in MLC. In the end, we evaluate the power consumption and IPC of MLC based main memory system and conclude that MLC can significantly reduce the overall energy dissipation. To unleash the potential of MLC as the main memory, architecture support such as MLC as memory extension is required in the future deployment.

Publication Date

3-29-2018

Publication Title

Proceedings - 2017 IEEE 15th International Conference on Dependable, Autonomic and Secure Computing, 2017 IEEE 15th International Conference on Pervasive Intelligence and Computing, 2017 IEEE 3rd International Conference on Big Data Intelligence and Computing and 2017 IEEE Cyber Science and Technology Congress, DASC-PICom-DataCom-CyberSciTec 2017

Volume

2018-January

Number of Pages

1180-1185

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/DASC-PICom-DataCom-CyberSciTec.2017.189

Socpus ID

85048097452 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85048097452

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