Design And Evaluation Of A Spintronic In-Memory Processing Platform For Nonvolatile Data Encryption

Keywords

Advanced encryption standard (AES); domain wall motion (DWM); in-memory processing platform; spin Hall effect (SHE)

Abstract

In this paper, we propose an energy-efficient reconfigurable platform for in-memory processing based on novel four-terminal spin Hall effect-driven domain wall motion devices that could be employed as both nonvolatile memory cell and in-memory logic unit. The proposed designs lead to unity of memory and logic. The device to system level simulation results show that, with 28% area increase in memory structure, the proposed in-memory processing platform achieves a write energy 15.6 fJ/bit with 79% reduction compared to that of SOT-MRAM counterpart while keeping the identical 1 ns writing speed. In addition, the proposed in-memory logic scheme improves the operating energy by 61.3%, as compared with the recent nonvolatile in-memory logic designs. An extensive reliability analysis is also performed over the proposed circuits. We employ advanced encryption standard (AES) algorithm as a case study to elucidate the efficiency of the proposed platform at application level. Simulation results exhibit that the proposed platform can show up to 75.7% and 30.4% lower energy consumption compared to CMOS-ASIC and recent pipelined domain wall (DW) AES implementations, respectively. In addition, the AES energy-delay product can show 15.1% and 6.1% improvements compared to the DW-AES and CMOS-ASIC implementations, respectively.

Publication Date

9-1-2018

Publication Title

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volume

37

Issue

9

Number of Pages

1788-1801

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/TCAD.2017.2774291

Socpus ID

85035086354 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85035086354

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