A Parity-Preserving Reversible Qca Gate With Self-Checking Cascadable Resiliency

Keywords

full adder; parity-preserving; Quantum-dot cellular automata; reversible logic; self-checking fault detection methodology

Abstract

A novel Parity-Preserving Reversible Gate (PPRG) is developed using Quantum-dot Cellular Automata (QCA) technology. PPRG enables rich fault-tolerance features, as well as reversibility attributes sought for energy-neutral computation. Performance of the PPRG design is validated through implementing thirteen standard combinational Boolean functions of three variables, which demonstrate from 10.7 to 41.9 percent improvement over the previous gate counts obtained with other reversible and/or preserving gate designs. Switching and leakage energy dissipation as low as 0.141 eV and 0.294 eV, for 1.5 E-k energy level are achieved using PPRG, respectively. The utility of PPRG is leveraged to design a one-bit full adder with 171 cells occupying only 0.19 \mu \text{m}^2 area. Finally, fault detection and isolation properties are formalized into a concise procedure. PPRG-based circuits capable of self-configuring active recovery for selected three-variable standard functions are realized using a memoryless method irrespective of garbage outputs.

Publication Date

10-1-2018

Publication Title

IEEE Transactions on Emerging Topics in Computing

Volume

6

Issue

4

Number of Pages

450-459

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/TETC.2016.2593634

Socpus ID

85058334137 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85058334137

This document is currently not available here.

Share

COinS