Stochastic-Based Synapse And Soft-Limiting Neuron With Spintronic Devices For Low Power And Robust Artificial Neural Networks

Keywords

artificial neural network; domain wall motion; Magnetic tunneling junction; soft-limiting neuron; stochastic computing

Abstract

We propose an innovative stochastic-based computing architecture to implement low-power and robust artificial neural network (S-ANN) with both magnetic tunneling junction (MTJ) and Domain Wall (DW) devices. Our mixed-model HSPICE simulation results have shown that, for a well-known pattern recognition task, a 34-neuron S-ANN implementation achieves more than 1.5 orders of magnitude lower energy consumption and 2.5 orders of magnitude less hidden layer chip area, when compared with its deterministic-based ANN counterparts which are implemented with digital and analog CMOS circuits. We believe that our S-ANN architecture achieves such a remarkable performance gain by leveraging two key ideas. First, because all neural signals are encoded as random bit streams, the standard weighted-sum synapses can be accomplished by stochastic bit writing and reading procedure. Second, we designed and implemented a novel multiple-phase pumping circuit structure to effectively realize the soft-limiting neural transfer function that is essential to improve the overall ANN capability and reduce its network complexity.

Publication Date

7-1-2018

Publication Title

IEEE Transactions on Multi-Scale Computing Systems

Volume

4

Issue

3

Number of Pages

463-476

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/TMSCS.2017.2787109

Socpus ID

85040038360 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85040038360

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